The present invention relates to an art of a time division multiplexing transmitter for transmitting time division multiplexed data, and more particularly, to an art for identifying a time slot of a reference channel contained in the multiplexed signal to extract a desired channel based on the phase difference between the time slots.
In order to select and extract a desired channel from among signals in which data of multiple channels are time division multiplexed, the time slot phase of the desired channel has to be identified.
Assuming that N (positive integer) channels are multiplexed, some of those channels are used as reference channels for identifying the time slot phase. A receiver side detects the reference channel from among the multiplexed signals and identifies the time slot phase. Based on a predetermined relative phase between the reference channel and the channel to be extracted, the desired channel is extracted.
FIG. 9 is a schematic view of a construction of a conventional time division multiplexing transmitter disclosed in a paper titled "Study on large-capacity digital video distribution system to Development on time division data multiplexing and distribution method with compact 10 Gbps optical terminal" written by Hajime ISHIKAWA et al. on "Technical Report of IEICE (EMCJ94-49(1994-11))".
The time division multiplexing transmitter comprises a transmission unit 101 for time division multiplexing data of N channels and converting the same into optical signals for transmission, an optical fiber 102 as a transmission path and a receiving unit 103 for extracting the desired channel among received signals for outputting.
The transmission unit 101 is described in detail.
Data 104 of M (M is a positive integer, M.ltoreq.N) channels of N channels are input to reference channel signal generators 105.sub.1, to 105.sub.M, respectively. The rest of the data signals 106 of (N-M) channels are input to a time division multiplexing circuit 107.
The reference channel signal generators 105.sub.1 to 105.sub.M are circuits for adding a different bit pattern as identification information to each data signal for transmission. The time division multiplexing circuit 107 time division multiplexes M data signals output from the reference channel signal generators 105.sub.1 to 105.sub.M and data signals 106. An optical transmitter 108 is a circuit for converting a signal output from the time division multiplexing circuit 107 into an optical signal for transmission.
The receiving unit 103 is described in detail.
An optical receiver 109 receives the optical signal transmitted from the optical transmitter 108 via the optical fiber 102. The optical signal is further converted into an electric signal 111. A clock extraction circuit 112 is a circuit for inputting the electric signal 111 and extracting a clock signal 113 at a frequency corresponding to the resultant bit rate. A frequency divider circuit 114 is a circuit for outputting a signal 115 obtained by frequency dividing the clock signal 113 into 1/k (k: natural number and prime in relation with M). A phase control circuit 116 is a circuit for outputting a synchronous signal 118 having a phase shifted from that of the signal 115 by the amount defined based on a phase control signal 117.
An decision circuit 119 is a circuit for extracting the data contained in the time slot having the phase corresponding to the synchronous signal 118 from the electric signal 111. Data signals 121 of one channel extracted by the decision circuit 119 are output to a reference channel detection circuit 122. The reference channel detection circuit 122 is a circuit for determining if a predetermined bit pattern as identification information is contained in the input data signals 121.
In order to detect the reference channel from among the multiplexed data signals, phase of the phase control circuit 116 is sequentially changed and data signal at every time slot is sent to the reference channel detection circuit 122. When detecting a reference channel generated by any one of the reference channel signal generators 105.sub.1 to 105.sub.M of the transmission unit 101, the reference channel detection circuit 122 identifies the phase of the synchronous signal as the reference channel phase. In order to extract a desired channel from among N channels, the phase control circuit 116 is designed to output a synchronous signal obtained by adding phase difference between the reference channel and desired channel to the reference channel phase.
Another conventional time division multiplexing transmitter has been disclosed in Japanese Patent Laid Open No. 291840 (1992), which is constructed such that a channel phase is determined by detecting a specific bit pattern for frame synchronization at each channel multiple times for protecting synchronization. In this prior art, frequency of bit pattern non-conformity is subtracted from frequency of the bit pattern conformity. If the resultant subtraction value is 5 or greater, synchronization state is detected.
In the above-mentioned conventional time division multiplexing transmitters, specific bit pattern as identification information is added to each reference channel, which is detected by a receiver side for determining the reference channel phase. Since the transmission data can use any bit pattern, the channel other than the reference channel may have the same bit pattern as that of the identification information, resulting in misidentifying such channel as the reference channel. Therefore it is necessary to provide rear protection for determining the reference channel after detecting the bit pattern as the identification information multiple times. The above process unnecessarily extends the time for determining the reference channel phase. In case a code error of the identification information occurs during transmission, the bit pattern is not detected correctly, thus deviating from synchronization.